Chemical Oxide Removal (“COR”) is a gaseous process known in the art to selectively etch oxides. In COR, gaseous ammonia (“NH3”) and hydrogen fluoride (“HF”) are reacted to produce NH4Fx, which reacts with silicon oxide on a semiconductor wafer to form ammonium hexafluorosilicate (“(NH4)2SiF6”). The semiconductor wafer is then heated, producing nitrogen (“N2”), water (“H2O”), silicon tetrafluoride (“SiF4”), and NH3, which are volatile and evaporate from the surface of the semiconductor wafer. Alternatively, the (NH4)2SiF6 is removed using a deionized (“DI”) water rinse. COR is marketed under the tradename CERTASE® by Tokyo Electron Limited. Additional NH3/HF-based chemistries for etching oxides are marketed by ULVAC Technologies, Inc. (Methuen, Mass.) and Applied Materials, Inc. (Santa Clara, Calif.). U.S. Pat. No. 6,951,821 discloses a method of trimming an oxide hard mask using a chemical treatment and a thermal treatment. The chemical treatment includes exposing the oxide hard mask to NH3 and HF. The thermal treatment includes heating the oxide hard mask to a temperature that ranges from 20° C.-200° C. The combination of the chemical treatment and the thermal treatment etches a thermal oxide at greater than 10 nm per 60 seconds of chemical treatment and tetraethyl orthosilicate (“TEOS”) at greater than 10 nm per 180 seconds of chemical treatment.
COR has also been used to selectively remove small amounts (1 nm-30 nm) of silicon oxides, such as a native oxide or a thermal oxide, relative to polysilicon. United States Patent Application Publication No. 2006/0196527 discloses using COR to remove SiO2 in a pre-metal-silicon contact formation cleaning, to remove SiO2 before a silicon epitaxial process, or to remove SiO2 from a polysilicon wafer before depositing a silicide metal.
U.S. Pat. No. 7,091,069 discloses using a plasma or vapor of HF and NH3 to remove a sacrificial oxide layer on a silicon-on-insulator (“SOI”) metal oxide semiconductor field effect transistor (“MOSFET”). U.S. Pat. No. 6,656,824 discloses using a plasma or vapor of HF and NH3 to remove a sacrificial oxide layer in a MOSFET. The plasma or vapor of HF and NH3 produces undercuts beneath silicon spacers formed on sidewalls of a dielectric layer of the MOSFET. U.S. Pat. No. 6,838,347 discloses etching concave portions of an oxide hardmask at a reduced rate relative to convex portions using a plasma or vapor of HF and NH3.
Shallow trench isolation (“STI”) has been commonly used in semiconductor fabrication to provide field isolation. As semiconductor devices are scaled ever smaller, and trenches become narrower, filling the trenches with a dielectric material becomes increasingly difficult. As trench sizes become smaller, seams, voids, gaps, or microbubbles are unavoidably formed in the trenches as the dielectric material is deposited. These seams, voids, gaps, or microbubbles affect the ability to uniformly etch the dielectric material. In addition, if the semiconductor device includes trenches having different widths, uniformly removing the dielectric material from the trenches is difficult. Furthermore, if the semiconductor device includes other exposed layers, removing the dielectric material without removing the other exposed layers is difficult.